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Axiado Corporation: Rtl/Soc Verification Engineer Ii

Axiado Corporation

This is a Full-time position in Ottawa, ON posted July 11, 2021.

Axiado is an AI-enhanced security processor company redefining the control and management of every digital system.

The company was founded in 2017, and currently has 35 employees.

At Axiado, developing great technology takes more than talent: it takes amazing people who understand collaboration, respect each other, and go the extra mile to achieve exceptional results.

It takes people who have the passion and desire to disrupt the status quo, deliver innovation, and change the world.

If you have this type of passion, we invite you to apply for this job.JOB OVERVIEWRTL/SoC Verification Engineerposition is your opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT.

You should have prior knowledge and experience with UVM verification and UVM environment development.

You will be responsible for RTL/SoC verification of ARM based CPUs, and work on industry-standard verification methodologies like UVM, Portable Stimulus and Formal verification flows.

You will report to the Director of Engineering.KEY RESPONSIBILITIESProject ExecutionHelp develop test plan definition; Micro-architecture design verification, RTL verification, and documentation; Block-level use-case verification; andSupport test program development, FPGA emulation, chip validation, and chip life until production maturity.Team BuildingCollaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.QUALIFICATIONS AND SKILLS2+ years of experience in UVM verification and UVM environment development; Experience in test plan definition and testcase development in C/Assembly/SystemVerilog; Expertise in verifying designs at RTL level and gate-level simulation; Good understanding of coverage analysis and use-case verification; Fluency with scripting languages (e.G., Perl, Python, Shell); Experience in functional test vector development and post-silicon bring-up/debug is a plus; andPreferred: knowledge of Power Aware verification is a plus.ACADEMIC CREDENTIALSBA or MS (preferred) degree in EE/EECS/CS or equivalent.